(1) Field of the Invention
The present invention relates to a method of fabricating a dynamic random access memory having an increased capacitance capacitor by incorporating a cylindrical electrode having a fin structure.
(2) Description of the Prior Art
In recent years there has been a dramatic increase in the packing density of DRAMs. Large DRAM devices are normally silicon based, and each cell typically embodies a single MOS field effect transistor with its source connected to a storage capacitor. This large integration of DRAMs has been accomplished by a reduction in individual cell size. However, the reduction in cell size results in a decrease in storage capacitance leading to reliability drawbacks, such as a lowering of the source/drain ratio and undesirable signal problems. In order to achieve the desired higher level of integration, the technology must keep almost the same storage capacitance on a greatly reduced cell area.
Efforts to maintain or increase the storage capacitance in memory cells with greater packing densities have included the use of a stacked capacitor design in which the capacitor cell uses the space over the device area for the capacitor plates. In their U.S. Pat. No. 5,444,010 to Park et al, the inventors describe a method of forming a stacked capacitor with a central recess on the planarized polysilicon layer. The top plate wraps under the storage electrode. U.S. Pat. No. 4,742,018 to Fazan et al shows a method of making a stacked capacitor having an I-shaped cross-section. U.S. Pat. No. 5,447,878 to Park et al teaches a method of forming a horizontally-finned auxiliary electrode underneath the main electrode.